The invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming inter metal dielectric films (IMD).
Advances in semiconductor manufacturing technology have led to the development of integrated circuits with multiple interconnect levels. In an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide.
A consequence of separating patterned conductive material with insulating materials, whether the conductive material is used on a single level or multiple levels, is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, unnecessary power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce unwanted capacitance is to increase the distance between the interconnects. Increased spacing between interconnect lines, however, has adverse consequences, such as increased area requirements and corresponding increases in manufacturing costs. Another way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant.
Typically a low k IMD layer comprises a barrier layer on a semiconductor substrate to avoid diffusion from the low k material to the semiconductor substrate. A typical dual damascene interconnect architecture requires a barrier layer, a lower IMD layer, a stop layer, an upper IMD layer and an anti-reflective layer. In the conventional method, the described films are formed in different chambers, and the substrate is heated and then cooled during transfer from one chamber to another. Thus, the substrate is subjected to at least five thermal cycles before a dual damascene architecture can be formed, which is a waste of thermal budget. An excessive number of thermal cycles also reduces throughput. Moreover; the Cu metallization reliability is affected by the thermal budget. A process which requires fewer thermal cycles and lower thermal budget is therefore desirable.
U.S. Pat. No. 6,060,404 discloses an in-situ deposition method for formation of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiOxNy stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber under low pressure, maintaining the low pressure following the deposition of the SiOxNy stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiOxNy stop layer. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.